> > Preferable frequency of generation should be greater
> > than 50 Khz.

> > I wish to have at least 8 bits of resolution PER
> > channel. meaning 256 levels of speed control

> Sounds like any chip with more than 8 I/O pins could do it in
> some form or fashion.  200khz of bandwidth (4x50khz) takes
> up only 4% of the available instruction cycles on a pic running
> at 20MHz

For 8-bits of resolution, (1E6/50k)/256 = 78.125ns/bit

A 20MHz PIC has an instruction cycle of 200ns, implying the
fastest speed at 8-bit resolution = (1E6/(0.2*256) = 19.5kHz
unless I've missed something out (it's been a long week). To
get 50kHz, a 40*(100/78.125) = 51.2MHz PIC

I've recently sketched up something similar with 4 channels at
9-bits for an upcoming project, and the only way I could think to
get around it was to use a 40MHz PIC + a couple of 50MHz
Scenixes (ic=20ns). The Scenixes know when time is available
to pick up some quick 4-bit parallel data from the PIC, which is
collecting sensor data and holding it ready for the Scenixes to
grab. On paper it should produce 4 channels of seamless PWM
from the Scenix from 0.05Hz up to several (hopefully 25+) kHz,
but it is still on the drawing board

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