>Now, if both the EEPROM based and RAM based CPLD's used a JTAG
>port to do the download/programming, what is the difference realy ?

Probably none, but I'm thinking that it is probably easier to update the
CPLD code this way rather then removing the CPLD and programming it.

>Is the "programming" of the EEPROM a more complicated JTAG-operation
>then the "loading" of the RAM ?

Again probably not. Thinking about it more though, I have a feeling that the
RAM based devices tend to use an SPI EEPROM interface for image downloading
as this is extremely simple.

>You also need a permanent storage in the PIC (EEPROM ?) for storing
>the CPLD firmware, of course. In the other case (EEPROM-CPLD) the
>storage could be in the PC application and the PIC just need a RAM
>buffer during download of the CPLD firmware.

True, and at the end of the day there may be no real advantage in going this
route. It just strikes me that the RAM based devices may be easier for
updating in the one-off situation.

>Since I might be issing something I don't currently know,
>I'd like to see it myself. Any pointers to one of these
>RAM based CPLD's ?

Sorry, no, not yet had occasion to get involved with them. However IIRC
Altera make them. Hmm, just looked at the Altera site, and this device
series almost looks made to do the Logic Analyser function.
http://www.altera.com/products/devices/serialcfg/scg-index.html
Is there some sneaky way of using any free memory as the logic state
collection memory?

It appears that the Xilinx Spartan and Virtex families are SRAM type FPGA's,
and they have app notes on downloading from a micro.

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