Alan B. Pearce wrote : > I would suggest trying to use one of the CPLD types that is RAM internally, > and gets downloaded from external eeprom, rather than one with EEPROM cells. > The PIC could then do the download at power up. > > One reason I see for going this way is saving the CPLD programming loop as a > separate operation. I think the RAM types effectively use a JTAG port for > loading as well though. Now, if both the EEPROM based and RAM based CPLD's used a JTAG port to do the download/programming, what is the difference realy ? Is the "programming" of the EEPROM a more complicated JTAG-operation then the "loading" of the RAM ? Note that if the PIC would have a JTAG routine anyway (for the RAM loading), that routine could just as well be used to re-load a CPLD EEPROM, not ? OK, loading the RAM might be faster then re-loading a EEPROM, but, as in this case, you maybe only has to do this once (a during a few "CPLD firmware upgrades"), the (possible) speed advantage doesn't matter that much. You also need a permanent storage in the PIC (EEPROM ?) for storing the CPLD firmware, of course. In the other case (EEPROM-CPLD) the storage could be in the PC application and the PIC just need a RAM buffer during download of the CPLD firmware. Since I might be issing something I don't currently know, I'd like to see it myself. Any pointers to one of these RAM based CPLD's ? Jan-Erik. -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics