----- Original Message -----
From: "Bob Axtell"
> Yes, just to bypass it. My experience with CPLDs and FPGAs hasn't been
> good, and I design them out whenever possible, unless they are VERY simple
> like the early GALs. I spent 6 tough weeks troubleshooting a
> noise-sensitive XYLINX design, uncovered a floating gate internal to the
> array, a problem with the chip itself. Had to reprogram the chip around
the
> bad gate section. To cause the problem repeatedly, had to make radiation
> gadgets (magnet wire loops with buzzing relays) held next to the PCB.

What family of xilinx was that part?  Was it a compiler issue or a die
problem?  I guess I'd be gunshy after something like that; but isn't it sort
of like abandoning all the microchip product line because of the now famous
18F1320 clock problem?  Not a critique, I'm sort of that way with motorola
after some parts allocation problems.

> Theoretically CPLD are marvelous devices, but when there is a problem
> inside, physically  moving San Francisco a foot further to the left is
> easier...
That might not be quite so difficult; just wait for the next big quake and
have nature do it for you.  :')

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