Yes, just to bypass it. My experience with CPLDs and FPGAs hasn't been
good, and I design them out whenever possible, unless they are VERY simple
like the early GALs. I spent 6 tough weeks troubleshooting a
noise-sensitive XYLINX design, uncovered a floating gate internal to the
array, a problem with the chip itself. Had to reprogram the chip around the
bad gate section. To cause the problem repeatedly, had to make radiation
gadgets (magnet wire loops with buzzing relays) held next to the PCB.
Theoretically CPLD are marvelous devices, but when there is a problem
inside, physically  moving San Francisco a foot further to the left is
easier...

BUT, if I could buy an already programmed PLCC device, I guess that's OK,
too, for a one-up project.

I think you have a good idea, Herbert. I made one years ago (8051), but
it's not deep enough for today's applications.

How do you display it on the PC?

--Bob




At 01:23 PM 11/17/2003, you wrote:
>I'm guessing they want to bypass the use of the CPLD. TTYL
>
> > Interesting.
> > What would be gained from that ?
> > Jan-Erik.
> >
> > Bob Axtell wrote :
> > > Is there anyway that you could send a PDF of the CPLD logic-equalivancy
> > > schematic? That way we non-XILINX folks can implement the logic
> > in SMD 74F
> > > logic...
> >
> > --
> > http://www.piclist.com hint: To leave the PICList
> > mailto:piclist-unsubscribe-request@mitvma.mit.edu
> >
>
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--------------
Bob Axtell
PIC Hardware & Firmware Dev
Tucson, AZ
1-520-219-2363
"I lose some on each sale but make it up in volume."

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