Herbert Graf wrote:

> The sample rate is fixed in hardware to 8 discrete steps: osc, osc/2,
> osc/4, osc/8, osc/16. osc/32, osc/64 and osc/128 IIRC, osc being the
> frequency of the oscillator feeding the CPLD.


Now, this might me asking a little to much, but I think
steps in the standard 1,2,5,10,20,50,100,200,500... series are
a little easier to "read" and interpret. It might also be easier
to build the timescale in the PC display application.

Well, as I said, it might be asking to much :-)

Jan-Erik.

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