Hi-
I have to support your position.  Let's go with what you have, or what
you are willing to do to 'improve' it, whether cheaper ram, or USB.  I
would appreciate a programmed CPLD, though ;-).
Also, I would appreciate a pcb.

I volunteer to help design the pcb (Eagle) - ie circuit checking etc.
David

Herbert Graf wrote:

>>A few thoughts.
>>
>>KISS (keep is simple stupid).
>>
>>
>
>        Actually it is quite simple in current form.
>
>
>
>>Use commonly available CHEAP memory. I you really want non volatile,
>>add your own lithium battery.
>>
>>
>
>        The memory I'm using was free, through Maxim's sample program, can't get
>cheaper then that.
>
>
>
>>Make it modular. 8/16/24/32 bits is basically an additional RAM device
>>and a tri state device to handle the data bus gating to the PIC
>>for readout.
>>
>>
>
>        Not that simple, the PIC is the device that triggers, there isn't enough
>I/O left on the PIC for 24 or more channels. You'd have to start
>multiplexing data lines, and that's starting to get complicated, or give up
>triggering on all channels. I'm not convinced 24 or more channels are even
>needed, I think you are forgetting the type of audience that would be
>interested in this sort of thing.
>
>
>
>>Why use a custom programmed CPLD when a common 'HC counter would
>>do as address generator?
>>
>>
>
>        3 reasons:
>
>        1. Speed, a CPLD is MUCH faster then discrete gates.
>        2. Size, the CPLD is more then just a counter, the SRAM requires certain
>signals to pulse at certain points in the clock waveform, it does more then
>address generation. It also has a selectable sample depth (where the counter
>stops), an 8 position clock divider and some clock muxes. Again, the number
>of chips required to do the same with discrete components starts to get a
>little silly.
>        3. Simplicity (which is your first thought), one chip handles all the "big"
>stuff, the PIC handles the rest.
>
>        I don't understand what's wrong with using a CPLD. It's SUCH an elegant
>solution, it's easy to get, it's easy to program, it's CHEAPER then the
>discrete solution, it's FAR more flexible, the software for it is FREE, I
>just don't get it. Discrete logic, in my mind, is dead.
>
>
>
>>All the address generator really needs is reset and autoincrement.
>>Easily handled by a bank of 74HC161's or the like. This makes the project
>>available to more people over the long term.
>>
>>
>
>        It does more then that, look at the verilog.
>        Plus, the 74 series is on the way out, it's far past being obsolete and the
>sooner it goes the happier many of us will be.
>
>
>
>>Some Video DRAMs have the address counter on board.
>>
>>
>
>        DRAM's usually require refreshing, again, too complicated. Also usually the
>packages are killers for hobbyists.
>
>
>
>>What about using common SDRAM? It's cheap, damned fast, and not that
>>hard to talk to. 128MBx64Bits is what, $80?
>>
>>
>
>        SDRAM requires refresh, has tons of pins, is hard to address (needs rows
>and columns), very specific in timing, and WAY WAY WAY overkill for this
>application. What are you going to do with 1GB of samples???
>
>
>
>>Is the point of this project to have a logic analyser (in which case
>>the "parallel port logic analyser" might be quicker/easier,
>>http://www.xs4all.nl/~jwasys/old/diy2.html
>>
>>
>
>        WAY WAY WAY slower, not as many channels, huge load on a system (due to
>polling), plus, have you ever done timing critical things with a PC parallel
>port and windows? Enough said. I built one like that, it's useful, but
>wasn't enough, for me.
>        Please note I'm not trying to knock the parallel port approach, I'm just
>saying it's not the in the same category.
>
>
>
>>or to make something with a PIC?
>>
>>
>
>        I already did.
>
>
>
>>An external programmable clock would allow one to use a PC ECP parallel
>>port at rates approaching 20Mhz (DMA mode).
>>
>>
>
>        Mine has an external programmable clock.
>
>        I think you've lost sight of things. This isn't a solution for a person
>looking for a 4Gsps 1TB sample depth logic analyzer. It's meant as an
>"inbetween", between parallel port type solutions and the "big guys".
>
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>
>

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