One question about this...would upping the CPLD frequency mean that to
capture slower circuits, a larger capture file is needed, as you can't
clock the capture from an external clock? Um...that might sound a bit
confusing. Essentially I mean that with a higher sampling frequency,
you'll get more time slices per given capture time. If you're working on
a slow circuit, won't this contribute to longer transfer periods?

Josh
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Herbert Graf wrote:
> > - Look over and verify the max logging frequency.
> >   (Herbert has run it in 4Mhz, but he says that up to
> >    40Mhz would be possible.)
>
>         I could be up for this one, it would just require dropping a different
> oscillator can in and making sure it captures properly.

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