> Hello Herbert.
>
> Having a look to your webpages i noticed you made a logic analyzer. Since
> I was interested in homebrewing mine as well, will you please give me some
> more details about your design? What is the max clock rate and how many
> channels, what about the trigger and displaying? I'd take the USB2
> way or (wich seems to me to be more difficult) the PCI interface. Let
> me know what you think about it... Many thanks.
>
> Ale

        That's actually a project I completed last year. I haven't had a chance to
complete the web page for it yet.

        Basically it uses a 16F877, a Xilinx CPLD and some SRAM. It's max speed
isn't really known, theoretically it COULD work up to about 40MHz in memory
serves (main limit is the access speed of the RAM used), I've never needed
to run it past 4MHz.
        The CPLD handles all the "high speed" stuff, i.e. address generation,
strobing, etc.
        The PIC acts as the control of the CPLD and tells it when to stop, when to
go, what clock speed to use, what sample depth, etc. The PIC also is one
which triggers. It can respond to any combination of levels, edges or don't
cares on any of the channels.
        The system is designed for 16 channels however I only have 8 enabled, never
needed more then 8! :)
        Details about it should be up within about a week, depending on how much
time I end up having to work on it. I also have other projects I'll be
posting soon but they'll take more time to post since they are older
projects and I don't remember much about them. TTYL

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