Sorry.
Forgot [OT]:

I'm wondering what the verdict would be if the dsPIC and the
56F8300 would be compared?

General purpose dsPIC:
    * Coming soon (TM)
    * FLASH 24 - 144 KByte. 8 - 48 Kprog
    * RAM 2048 - 8192 Byte
    * 16 working gegisters. 16 bit each
    * Two 40 bit DSP accumulators
    * Hardware DO and REP loops
    * 40, 44, 64 and 80-pin packages to fit a wide range of
I/O requirements
    * 16-bit timer/Input capture/output compare/standard
PWMs
    * 12-bit A/D=92s in 8 or 10 channel options
    * Multiple Serial Interfaces
          o CAN
          o UART
          o SPI
          o I2C

56F8300:
56F8323 Features:
    * On-chip memory includes high-speed volatile and
nonvolatile components:
          o 32KB of Program Flash
          o 4 KB of Program RAM
          o 8 KB of Data Flash
          o 8 KB of Data RAM
          o 8 KB of Boot Flash
    * Up to 60 MIPS at 60 MHz execution frequency
    * DSP and MCU functionality in a unified, C-efficient
architecture
    * JTAG/EOnCE for unobtrusive, real-time debugging
    * Four 36-bit accumulators
    * 16- and 32-bit bidirectional barrel shifter
    * Parallel instruction set with unique addressing modes
    * Hardware DO and REP loops available
    * Three internal address buses
    * Four internal data buses
    * Architectural support for 8-, 16- and 32-bit
single-cycle data fetches
    * MCU-style software stack support
    * Controller-style addressing modes and instructions
    * Single-cycle 16 x 16-bit parallel
multiplier-accumulator (MAC)

Regards Eelco.

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