>> Just plain cost of a piece of silicon doesn't matter.
>> And even from this point of view FPGA, CPLD are manufactured
>> with 0.13, 0.11, even 0.09 technology, not with 0.7, 0.5, 0.35
>> like PICs. Thus die space for FPGA, CPLD is much less.
>
>Careful there Mike, it's far more complicated then that.

Yeah, I agree with Herbert. Not only do you need space for the cell on the
FPGA, but you also need a lot more room for the configurable interconnects,
and the control of those interconnects. I am not a chip designer, but I
suspect that the finer technology advantage very soon gets eaten up this
way, giving you little advantage in die size for a given functionality.

>While actual physical die space may be smaller in the case you
>quote, cost of development and manufacturing is FAR higher. The
>cost of producing a piece of silicon using a 0.7 process is MANY
>magnitudes less then the cost of developing and manufacturing
>something at 0.09.

That is one factor. Also when you have a lot of interconnects your testing
time will rise considerably as well, to verify that all the interconnects
will work at rated speed.

>The fact of the matter is that, for similar functionality, an FPGA
>(or other "reconfigurable" logic) is more expensive then dedicated
>silicon. For a one off or low volume product this is a none issue.
>For a product where every cent counts, and volume is king, this is
>a BIG difference. TTYL

That is another factor, but there is yet another factor again. Who would
realistically fit a 48 pin QFP package reconfigurable device where something
like a 16F628 or smaller would be quite satisfactory in terms of computing
power and I/O lines? It is one thing to do this when building something for
oneself out of what you have in your spare bits, but to do it for a
manufacturable item is another thing. One of the reasons that there are so
many variants in the PIC line is the old "horses for courses" thing. I would
like to see even more variants, e.g. two hardware uarts, but no MSSP in some
of the 28 pin and smaller devices.

Unfortunately it appears from some of the errata that we have seen mentioned
here in the recent past, things have not been tested properly before
release, and/or the scaling down of the die has not worked correctly.
Possibly some of these have been rushed into production. At least they
seemed to have held off with the dsPIC so they get it working right :)

--
http://www.piclist.com hint: The PICList is archived three different
ways.  See http://www.piclist.com/#archives for details.