> > Same thing on serial bit rates. Both of you can't be 6% off in opposite
> > directions, but one of you can.
>
> Actually 5.8% error is the guaranteed to fail threshold assuming 1 start
> bit and 8 data bits.  In reality, total receive/transmit clock error more
> than half that is not a good idea.

SUMMARY    When sending 7 bit ASCII data a substantial increase in clock
speed error margin may be had by simply setting the unused MSB to 1 (!)
Somewhat more error margin again may be available by then slightly
increasing the sending clock speed.

(Maybe everyone already knew this?)

DETAIL:

I've done that calculation often before and did it again now just for
interest.
The difference from 5.8% is so small that it wasn't worth commenting on BUT
I suddenly realised there was a special but common case where a small but
possibly useful gain could be made.

**** This is worth thinking about for RC clocks and ASCII data ****

Assume an ideally timed receiver and a fast or slow sender.
The following is ideal and will be worse in practice.

Normally, in the limiting case, the sender can be too fast such that the
START of the STOP bit is sampled instead of the middle by the receiver .
This occurs when it sends 10 bits (1 start + 8 data + 1 stop ) in the time
that it SHOULD have sent 9.5 (1 start + 8 data + 1/2 the final start bit) so
it is fast by 10/9.5 = 5.26%. OK so far. (An assumption with a limiting case
fast sender is that the receiver is ready to receive a new start bit
IMMEDIATELY the "centre" of the prior STOP bit has been sampled. If this is
not the case then calculations will be slightly different. Technically a
STOP bit should last a full bit time although in practice a STOP half bit is
usually adequate for a perfectly timed system. No systems are perfectly
timed).

In the other limiting case the sender is slow such that it sends only 9 bits
(1 start + 8 data) when it should have sent 9.5 (1 + 8 + 0.5). It is slow by
9/9.5 = -5.26% (again).

HOWEVER if sending ASCII only 7 bits are used. If the 8th bit is set to
always 1 then, as this bit is sent last, if this bit is sampled by the UART
instead of the STOP bit due to excessively fast transmission, no error will
occur. The sender can be fast by 9.5/8 = 18.75% !!!
This is the same as sending 7 bit data with 2 stop bits. By centring the
data signal in the now wider tolerance band we get a greater error
tolerance. Regrettably it's not as good as the above figure suggests.
Whereas previously the critical point for fast senders was the leading edge
of the stop bit, it now becomes the leading edge of the 7th data bit. A fast
sender may now send 1+7 bits in the time that it should have sent 1+ 6.5.
The error allowed is 1 - 7/6,.5 = 7.7%.

Far less than the possible 18.75% but still 46% better (1 - 7.7/5.26) than
the case when 8 bit data is being sent.

Conclusion: When sending 7 bit ASCII data with an RC clock, significant
improvements in error tolerance can be had by increasing the clock speed
slightly. (Actual value left as an exercise for the student ;-) ).

BUT WAIT THERE'S MORE.
(Do they say that in your ads?)
If you can guarantee that the drift in speed is all one way (eg increases
with temperature) then you can skew your original clock speed positioning to
make better use of the new wider error tolerance. This is especially
applicable if you have a crystal clock at one end and RC at the other.This
may be excessive effort compared with eg using a ceramic resonator but may
pay dividends in some cases.

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads