Russell,
> FETS needs high peak gate drive currents to get good switching times. Your
> circuit uses only the 1K gate pull down to turn the FET off which will
lead
> to very slow turn off times.

Firstly, thanks for your replay. You've just anticipated the next stage of
my debugging process. I've modified my diagram with your solution. But the
problem has to do more with CTR than the gate discharge. I have measured the
pulse before and after the opto. It looks like 6 us wider, 3us slope each
side of the pulse.
The frequency used is 20Khz, given a 50us period. When pwm approaches to
maximum value, say, 0x300 (of 0x3ff module max value) is the same as if it
where 0x3ff. So I thought about to change the opto or enlarge the period,
the
last solution is not allowed.

Anyway you have anticipated to my next problem giving me the solution.
Thanks again. I will try 6n137, 30ns response!

Dennis.

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