--=====================_452417890==_ Content-Type: text/plain; charset="iso-8859-1"; format=flowed Content-Transfer-Encoding: quoted-printable I'm confused. I don't see any I2C routines in this code. I'm including Microchip's standard inclusion for Single-Master I2C. Its very fast and small. You can remove almost all delays if you are running below 4mhz. Change the port type (PORTA, PORTB, etc) to whichever is used in your= routine. --Bob At 03:59 PM 8/31/2003 +0200, you wrote: >Hello! > >I=B4m trying to use a F84 as master and send >data to a 24C02 but I don=B4t have any good >result! >I=B4m wonder if anyone has any experience >of that and want to help me out! > >Regards > >=C5ke Neehr > >-- >http://www.piclist.com hint: The list server can filter out subtopics >(like ads or off topics) for you. See http://www.piclist.com/#topics > -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics --=====================_452417890==_ Content-Type: text/plain; charset="us-ascii" Content-Disposition: attachment; filename="MC_I2C.TXT" ;*************************************************************************** ;*************************** EEPROM Subroutines ************************** ;*************************************************************************** ;*************************************************************************** ; Communication for EEPROM based on I2C protocol, with Acknowledge. ; WRITE_BYTE: Byte write routine ; Inputs: EEPROM Address EEADDR ; EEPROM Data EEDATA ; Outputs: Return 01 in W if OK, else return 00 in W ; ; READ_RAND: Read EEPROM byte at supplied address ; Inputs: EEPROM Address EEADDR ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W ; ; Note: EEPROM subroutines will set bit 7 in PC_OFFSET register if the ; EEPROM acknowledged OK, else that bit will be cleared. This bit ; can be checked instead of refering to the value returned in W ;*************************************************************************** ;********************** Set up EEPROM control bytes ************************ ;*************************************************************************** write_byte movlw b'10000000' ; PC offset for write byte. EE_OK: bit7 = '1' goto init_write_control ; read_byte movlw b'10000011' ; PC offset for read random. EE_OK: bit7 = '1' ; init_write_control bcf flags,0 movwf pc_offset ; Load PC offset register, value preset in W movlw b'10100000' ; Control byte with write bit, bit 0 = '0' start_bit bcf portb,sda ; Start bit, SDA and SCL preset to '1' ;******* Set up output data (control, address, or data) and counter ******** ;*************************************************************************** prep_transfer_byte movwf eebyte ; Byte to transfer to EEPROM already in W movlw 8 ; Counter to transfer 8 bits movwf tmp bank1 bcf trisb,scl ;both outputs bcf trisb,sda bank0 ;************ Clock out data (control, address, or data) byte ************ ;*************************************************************************** output_byte bcf portb,scl ; Set clock low during data set-up rlf eebyte, f ; Rotate left, high order bit into carry bit bcf portb,sda ; Set data low, if rotated carry bit is btfsc status,c ; a '1', then: bsf portb,sda ; reset data pin to a one, otherwise leave low clrwdt bsf portb,scl ; clock data into EEPROM decfsz tmp,f ; Repeat until entire byte is sent goto output_byte nop ;************************** Acknowledge Check ***************************** ;*************************************************************************** bcf portb,scl ; Set SCL low, 0.5us < ack valid < 3us nop bsf portb,sda bank1 bsf trisb,sda ;input bank0 goto $+1 ; May be necessary for SCL Tlow at low voltage, bsf portb,scl ; Raise SCL, EEPROM acknowledge still valid btfsc portb,sda ; Check SDA for acknowledge (low) bsf flags,0 ; If SDA not low (no ack), set error flag bcf portb,scl ; Lower SCL, EEPROM release bus btfsc flags,0 ; If no error continue, else stop bit goto stop_bit bank1 bcf trisb,sda ;output bank0 ;***** Set up program counter offset, based on EEPROM operating mode ***** ;*************************************************************************** movf pc_offset,w andlw b'00000111' ;was b'00001111' addwf pcl,f goto init_address ;PC offset=0, write control done, send address goto init_write_data ;PC offset=1, write address done, send data goto stop_bit ;PC offset=2, write done, send stop bit goto init_address ;PC offset=3, write control done, send address goto init_read_control ;PC offset=4, send read control goto read_bit_counter ;PC offset=5, set counter and read byte goto stop_bit ;PC offset=6, random read done, send stop ;********** Initalize EEPROM data (address, data, or control) bytes ****** ;*************************************************************************** init_address incf pc_offset,f ; Increment PC offset to 2 (write) or to 4 (read) movf eeaddr,w ; Put EEPROM address in W, ready to send to EEPROM goto prep_transfer_byte init_write_data incf pc_offset,f ; Increment PC offset to go to STOP_BIT next movf eedata,w ; Put EEPROM data in W, ready to send to EEPROM goto prep_transfer_byte init_read_control bcf flags,0 ;might have been toggled bsf portb,scl ; Raise SCL nop bsf portb,sda ; raise SDA incf pc_offset,f ; Increment PC offset to go to READ_BIT_COUNTER next movlw b'10100001' ; Set up read control byte, ready to send to EEPROM goto start_bit ; bit 0 = '1' for read operation ;************************** Read EEPROM data ***************************** ;*************************************************************************** read_bit_counter bsf portb,sda nop bsf portb,scl ; set data bit to 1 so we're not pulling bus down. movlw 8 ; Set counter so 8 bits will be read into EEDATA movwf tmp bank1 bsf trisb,sda bank0 read_rand clrwdt bsf portb,scl ; Raise SCL, SDA valid. SDA still input from ack bsf status,c ; Assume bit to be read = 1 btfss portb,sda ; Check if SDA = 1 bcf status,c ; if SDA not = 1 then clear carry bit rlf eedata, f ; rotate carry bit (=SDA) into EEDATA; bcf portb,scl ; Lower SCL bsf portb,sda ; reset SDA decfsz tmp,f ; Decrement counter goto read_rand ; Read next bit if not finished reading byte bsf portb,scl nop bcf portb,scl ;****************** Generate a STOP bit and RETURN *********************** ;*************************************************************************** stop_bit bank1 bcf trisb,sda ; set SDA as output bank0 bcf portb,sda ; SDA=0, on TRIS, to prepare for transition to '1' bsf portb,scl ; SCL = 1 to prepare for STOP bit goto $+1 ; 4 NOPs neccessary for I2C spec Tsu:sto = 4.7us goto $+1 bsf portb,sda ; Stop bit, SDA transition to '1' while SCL high return ;Note: SDA and SCL still being driven by master, both set to outputs. ;**************************************************************************** ;*************************************************************************** ;*************************************************************************** -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics --=====================_452417890==_ Content-Type: text/plain; charset="us-ascii"; format=flowed -------------- Bob Axtell PIC Hardware & Firmware Dev Tucson, AZ 1-512-219-2363 -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics --=====================_452417890==_--