>> Is the ISR modifying the bank select register?
>
> !!! I think I'm onto something!

This is a perfect example the true problem being very different than what
the original poster was asking about.  This is why everything is and should
be suspect and up for reexamination when someone is asking for help about a
bug.

> The ISR saves 'W', 'STATUS',
> 'FSR' etc. into temp variables that are defined in Bank 0.

The W save area needs to be either reserved at the same offset in all banks,
or reserved in the unbanked memory many PICs have in the last 16 bytes of
each bank.  I do the latter.  The remaining state can be saved in a
particular bank because STATUS can be altered after W is saved and STATUS
then moved into W.  I put the save area for the other state in bank 0 so
that the new bank can be set in the ISR with the single instruction CLRF
STATUS.

There is no need to reinvent the framework for an interrupt service routine.
I believe there are several examples out there, including the QQQ_INTR.ASPIC
module of my PIC development environment at http://www.embedinc.com/pic.
All the state save/restore code is already there, and even automatically
configures itself per machine as to whether PCLATH is saved/restored.  It
also allows you to set a single assembly time switch at the top to indicate
whether FSR should be saved/restored in the interrupt service routine (it
only needs to be if FSR is used in the ISR).


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