Hi Dwayne, I think Bob just rounded up 3.4 Mbit/s to 4 MHz out of convenience (I think). High-speed mode (Hs-mode), with a bit rate up to 3.4 Mbit/s was added in version 2.0 of the spec in 1998. Version 2.1 of the spec came out in 2000. Regards, Ken Pergola -----Original Message----- From: pic microcontroller discussion list [mailto:PICLIST@MITVMA.MIT.EDU]On Behalf Of Dwayne Reid Sent: Friday, August 22, 2003 9:59 PM To: PICLIST@MITVMA.MIT.EDU Subject: Re: [EE]:I2C to diff Vdd chips At 08:33 AM 8/22/2003, Bob Axtell wrote: >My biggest concern with open collectors is (1) higher overall current drain >and (2) loss of speed. The original spec called for 100Khz clock speeds. >MANY I2C devices can operate at 4Mhz now. IIRC, hi-speed I2C is 400 KHz, not 4 MHz. Factor of 10 slower makes a huge difference! dwayne -- Dwayne Reid Trinity Electronics Systems Ltd Edmonton, AB, CANADA (780) 489-3199 voice (780) 487-6397 fax Celebrating 19 years of Engineering Innovation (1984 - 2003) .-. .-. .-. .-. .-. .-. .-. .-. .-. .- `-' `-' `-' `-' `-' `-' `-' `-' `-' Do NOT send unsolicited commercial email to this email address. This message neither grants consent to receive unsolicited commercial email nor is intended to solicit commercial email. -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details. -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.