Hmm, you're right Michael, noise immunity WILL suffer, since the I2C parts
swing at 0.7VCC for a guaranteed HI and 0.3VCC for a guaranteed low. (24C00
used as a reference).

My biggest concern with open collectors is (1) higher overall current drain
and (2) loss of speed. The original spec called for 100Khz clock speeds.
MANY I2C devices can operate at 4Mhz now.

--Bob

At 08:19 AM 8/22/2003 +0100, you wrote:
> > -----Original Message-----
> > From: Olin Lathrop [SMTP:olin_piclist@EMBEDINC.COM]
> > Sent: Friday, August 22, 2003 12:28 AM
> > To:   PICLIST@MITVMA.MIT.EDU
> > Subject:      Re: [EE]:I2C to diff Vdd chips
> >
> > > I2C master running on 3.3V, talking to various devices also running on
> > > 3.3, BUT one device is running off the 5V rail.
> > >
> > > Are there any issues involved with talking to the 5V device or do I need
> > > to interface 3.3/5 ?
> >
> > IIC is defined to make this possible.  Just tie the pullups to the 3.3V
> > line, not the 5V line.
> >
>Although it will most likely work (with reduced noise immunity), I don't
>beleive this was the intention of the I2C spec.  In fact, the Phillips
>specification ("The I2C-Bus specification" V2.1 January 2000) shows a simple
>method of interfacing 3 and 5 volts buses using a MOSFET of the SDA and SCL
>lines which gives a full voltage swing on both sides of the bus.
>
>Regards
>
>Mike
>
>
>
>
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--------------
Bob Axtell
PIC Hardware & Firmware Dev
Tucson, AZ
1-512-219-2363

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