>Bob Ammerman wrote:

> What is the state of the IRP bit in STATUS?

Upon startup, I always do:
    bcf    STATUS, RP0
    bcf    STATUS, RP1
I've not touched the IRP bit directly, but I believe it's supposed to
power-up as '0'.

and
>Nigel Orr wrote

>> ...
> >     incf        INDF  ; Increment the value at register ((contents of
> > location 0xA0)+0xA0)
...
> > Where is B1_COUNT initialised?

prior to this instruction, B1_COUNT was initialized to 0 (long before the
1st call to 'foo').
(sorry, perhaps my code snipped was indeed too brief!)
FSR=0xA0.  Doing 'incf INDF' should increment the contents of 0xA0, and the
result should
be 0xA0 contains 0x01.

and,
> Picdude wrote:
> Just a quick glimpse thru this, I'm wondering whether the destination on
the
> "incf INDF" instruction makes a difference?

That's the gist of what I was thinking, too.   As I pointed out in the
original post, this behavior is *sporadic*... meaning that I see different
results on multiple "power-on, same steps + same data" sequences.  At first
it seemed that it must be a case of FSR getting clobbered during ISR, but
that's not happening.
My understanding is that to access Bank 1 data memory, the upper bit of the
address set in FSR (e.g. 0xA0) being a '1' will effectively do the bank
selection without having to muck with STATUS/RP0.

Thanks to everyone for the ideas... I'm going to try to instrument things a
bit more closely; will let you know what I find!

Jim
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