Andre,
This may have already been discussed, but I was curious as to what you need
such a precise (and seemingly arbitrary) time value for?
Denny


----- Original Message -----
From: andre abelian <engelec@EARTHLINK.NET>
To: <PICLIST@MITVMA.MIT.EDU>
Sent: Tuesday, August 05, 2003 3:50 PM
Subject: Re: [pic]: timing calculation error


> Olin,
>
> Thanks for your replay.
> I guess mastering (interrupt service routine) is not easy
> Even I get precise timing after adding more codes
> Timing gets changed more adjustments needed more changes needed
> I also found one more problem with mplab 6.22.
> Using same code with mplab 6.22 will generate different timing on timer0
> then mplab 6.30 does.
>
> Andre
>
>
>
>
> -----Original Message-----
>
> > Try again.
>
> Definitely better.
>
> > I am generating 46.25 us interrupt and this is how I calculated.
> > Using 16 mhz crystal with 8 bit timer 256(8 bit timer)-185(the value I
> > use)=71 so if I put 71 in timer0 I should get 185/4=46.25 us
> interrupt.
> > Now since there are timer0  (2 cycle) latency + interrupt (5 cycle)
> > latency now real number should be 71-2-5=64 so if I put 64 in timer0 I
> > should be able to get 46us but I am not getting 46us. By adjusting the
> > number to 119
>
> Don't try to account for the interrupt latency.  It is much better to
> add
> a fixed value into timer 0 each interrupt.  16MHz clock means 4MHz timer
> 0
> increment rate (assuming prescaler of 1).  1 / 4MHz = 250nS, which is
> the
> timer 0 tick period.  46.25uS / 250nS = 185 timer 0 increments in your
> desired interrupt period.
>
> Left alone, timer 0 will cause an interrupt ever 256 ticks.  If you add
> into TMR0, it misses 2 ticks, effectively making it 256 + 2 = 258 ticks
> per interrupt.  258 - 185 = 73 too many ticks per interrupt period.
> Therefore, you will achieve a 46.25uS interrupt period by adding 73 into
> TMR0 each interrupt.
>
> This assumes the prescaler is set to 1:1, meaning it must be assigned to
> the watchdog timer instead of timer 0.  Of course the accuracy is
> proportional to the accuracy of the CPU oscillator.
>
>
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