At 01:19 PM 7/24/2003 -0400, you wrote:
>SO the SPI clock provide input to a 555 timer, and the timer output is
>governed by this?

Each negative-going edge is pulse-stretched to 50-100msec in order to
make a visible LED blink. That way you don't miss a transfer that might only
take a microsecond or two.

>I guess this on provides a way of knowing that there's clock on the SPI bus,
>whereas ideally I wanted to see Tx/Rx.

To see the whole thing you'll need to look at /CS for the device as well
as SDI/SDO (probably with a pullup on the tristate SDO). Logic analyzer
territory.

But data can only pass on the bus when SCK is active, and SCK will idle
(typically low) when the master is not sending or receiving.

>But it's an interesting soluton (and a very nice ASCII schematic!) :-)

Thanks!

Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

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