> The data sheet of 16F876A specifies (in section 14.4) that MCLR
> should not be connected directly to VDD.

Section 12.4, the section on POR, of the 16F87x d/s (DS30292B)
conflicts with that

> Any idea what is the reason ?  The absolute max rating specifies that
> MCLR can go to VDD level.

Possible reasons not to tie MCLR to Vdd

- power-up stabilisation (as mentioned in POR description)

- isolating MCLR from PSU spikes with an RC filter

- tying MCLR directly to Vdd prevents the use of an external reset
  (or being able to assign MCLR as a GP input pin)

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