> -----Original Message-----
> From: Rick Regan [SMTP:rdrdr2k@YAHOO.COM]
> Sent: Friday, June 27, 2003 8:32 PM
> To:   PICLIST@MITVMA.MIT.EDU
> Subject:      Re: [PIC]: SPI clock pulse width
>
> You've attached code for an SPI MASTER.  I was
> asking about an SPI SLAVE.  If you have matching
> SPI slave code that works with your bit-banged master
> clock pulse I'd like to take a look.
>
> In any case, the answer for me is simple.
> I just needed to slow the master clock down enough so
> my inefficient C code slave could process each in/out
> bit within the clock period.  I did this by
> configuring the master to use TMR2 as a timing source.
> I was more interested in learning the protocol than
> making it fast.
>
Ah, sorry for that, I obviously didn't read your original post very
carefully.

As I see it, you have two choices, either poll the clock and data or use
interrupts. Polling would undoubtedly be faster, but with far more overhead.
SPI devices usualy clock data on the rising edge, so you need to detect a
low follwed by a high state, then read data. Something like this should be
relatively quick:

while(CS) continue;     // wait for chip select to go low

while(SCK) continue;    // wait for clock to go low
while(!SCK) continue;   // wait for clock to go high
if(SDI) SpiData |= 0x80;                // set first bit

while(SCK) continue;    // wait for clock to go low
while(!SCK) continue;   // wait for clock to go high
if(SDI) SpiData |= 0x40;                // set second bit

....                                            // repeat for each bit


In HiTech PICC this produces the following code that takes 6 cycles per SPI
bit:

;TEST1.C: 15: while(RB0) continue;
l5
btfsc   6,0
goto    l5
;TEST1.C: 16: while(!RB0) continue;
l8
btfss   6,0
goto    l8
;TEST1.C: 17: if(RB1) SpiData |= 0x80;
btfsc   6,1
bsf     _SpiData,7


Regards

Mike








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