--- "D. Jay Newman" <jay@SPRUCEGROVE.COM> wrote:
> The clock pulse varies as the timing varies. The SPI
> clock is based on
> the master processor's clock on every system I've
> seen.

   Yes, that makes sense.  I was using FOSC/64 when
I measured the timing.  I suppose if I used FOSC/4,
the pulse width would be 1/2 usec (assuming 4Mhz
clock)?

> I would say the data pulse should start *just* after
> the clock pulse
> and end just after the clock pulse.
>
> The recieving device should not depend on speeed;
> all of this is
> controlled by the master. There are some really good
> timing diagrams
> in the datasheets of the PICs.

   I see that in the timing diagrams the pulse width
appears equal to the time between pulses (i.e.,
50% duty).  If that is the case, then I can compute
the width from the FOSC/x setting.

> You shouldn't need to know the pulse width, but some
> slaves specify
> the fastest speed the master's clock is allowed to
> go.

  In this case I am writing the slave (on another
PIC16F877), so I think I need to know the width.
I want to make sure I can detect the pulse by polling,
and send/receive the data before the next pulse.
It looks like in order to do that, I need to set the
master's clock rate high enough.

> I hope this helps.

  Thanks, it does.

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