On Thu, 26 Jun 2003, Daniel Serpell wrote:

> On Thu, Jun 26, 2003 at 05:43:23AM +0100, Sergio Masci wrote:
> > If I understand correctly you are clocking in all bit 7's followed by all bit
> > 6's down to all bit 0's
> >
> > Try the following:
> >
> >         acc = 0
> >
> >         for (int j=0; j<8; j++)
> >         {        acc = (acc << 1) + count_one_bits(read_port())
> >         }
> >
> > count_one_bits() could be implemented as a lookup table
>
> It's more efficient to do directly. Each loop iteration can be
> done in 15 cycles, if you unroll it and add the "acc=0" at the
> begining, you get 15*8+1 = 121 cycles (and 121 program words).
>
> Seems that it's the faster version.

I agree, it is faster. Good observation Sergio. For the 18f family, I
think you only need about half of those 121 cycles.

If the count_one_bits is a program memory table for the 18f family then
TABLATH can be preloaded with the (256 byte-aligned) high word of the
table address. Then to count the ones do this:


init:
       MOVLW  HIGH(count_one_bits_table)
       MOVWF  TABPTRH
       CLRF   TABPTRU

       return


clock_in_data:

       MOVF   acc_lo,W       ; acc <<= 1
       ADDWF  acc_lo,F
       RLFCF  acc_hi,F

       MOVFF  IOPORT,TABPTRL ; count the ones
       TBLRD  *
       MOVF   TABLAT,W       ;


       ADDWF  acc_lo,F
       MOVLW  0
       ADDWFC acc_hi,F

  ;----
  ;   check if this was the 8'th bit
  ;   ....



That's 10 cycles (9 instructions) per iteration. If you concatenate all 8
samples together, then the total cycles are 66. The first sample
can be written like this:


       MOVFF  IOPORT,TABPTRL ; count the ones
       TBLRD  *
       MOVF   TABLAT,W
       CLRF   acc_hi
       CLRC

The second through eighth  can be written like:

       RLCF   wreg,F
       RLCF   acc_hi,F
       MOVFF  IOPORT,TABPTRL ; count the ones
       TBLRD  *
       ADDWF   TABLAT,W
       SKPNC
        INCF  acc_hi,F       ;(note, this clears C in the 18F family)

followed by a

       MOVWF  acc_lo

at the end. However, I imagine that there has to be some kind of hand
shaking between each bit-sample. For example, you can intersperse clock
toggles:


      MOVFF IOPORT,TABPTRU        ; read the data port

      bsf   CLK_PORT,CLK_BIT      ; tell the babies to spew the next bit

      TBLRD *
 ... count the bits etc


      MOVFF IOPORT,TABPTRU        ; read the data port

   ; clock on falling edge

      bcf   CLK_PORT,CLK_BIT      ; tell the babies to spew the next bit


This adds 8 more cycles. A bigger issue is whether the 12-bit cores can
even keep up with this kind of clock speed. The'll need 3 cycles just to
sample the clock and 4'th to but the new data and another 2 to set up for
the next clock.


BTW, The reason you want to align the 256 byte table to a 256-byte
boundary is because that saves 16-bit arithmetic when computing the
address into the table.


Scott

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