On Thu, Jun 12, 2003 at 04:31:49PM +0000, Daniel Sweet wrote:
>
> When at 40Mhz it always locks into exactly the same point of the
> cycle. I am not 100% certain that this will be the correct cycle
> but from what I have seen using a 40Mhz oscillator module it should
> be. Or have I misuderstood what you are saying? Can you explain a
> little more?

The PIC divides internaly the EC clock by 4, so you can't reliably known
on wich phase you are locked, ej:

EC    __--__--__--__--__--__--__--__--__...

p1    __----____________----____________...
p2    ______----____________----________...
p3    __________----____________----____...
p4    ______________----____________----...

PIC   ..11111111111111112222222222222222...
Cicle

(p1-p4 are the internal phases of the PIC's clock).

The start of the pic cycles can be on any edge of the EC clock. The
problem is the same as using the PIC's internal PLL.

> It has to be locked to the 15.625Khz Hsync coming from the camera
> (via sync separator) as this signal does vary and causes all sorts
> of picture wobble. I do generate hsync in the PIC exactly and have
> tried to feed this into the ext divide of the Genlock IC to stabilise,
> but the one I generate is too perfect when compared the camera sync
> and the differences between them are too great for my PLL to correct
> them (don't know how well i explanied that, hope it makes sense)

Well, I was saying that you can lock the signal generated by the PIC
to the external Hsync by varying the PIC's own clock:

                      +-----+
   External Hsync >---+     |
                      | PLL +-----> to PIC's clock.
   PIC gen. Hsync >---+     |
                      +-----|

This way, you ensure that the two are in sync. You have to use a
phase locked PLL (freq lock is not enought).

The oter way, as someone suggested is driving the PIC's MCLR to
ensure correct sync, perhaps you could reset it each field at the
exact time.

    Daniel.

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