Have been racking the old grey mush to come up with a way of determining if its out of phase, and then forcing the issue. Can't find anyway to detect it apart from visual (icould just tell the operate to cycle power untilit works but......!)

Have looked at the HS mode phase start up and it is consistently good, will  do some experiments to see if EC is the same.

Thanks for the comments,
DAN
>
> From: "M. Adam Davis" <adampic@UBASICS.COM>
> Date: 2003/06/12 Thu PM 04:50:32 GMT
> To: PICLIST@MITVMA.MIT.EDU
> Subject: Re: [PIC]:3rd Overtone- Now: [Pic]: HS/PLL issues when Genlocking to Video sync
>
> If you turn off the power up timer, and use EC mode without the PLL,
> then there is no startup timeout.  When the MCLR goes high, the next
> clock transition is the first one the processor uses.
>
> If you can't go backwards as Daniel Serpell suggests (syncing the video
> clock to the processor) then you might try some experiments with what
> phase the processor starts in with an exernal clock.
>
> Alternately you can force the issue - start the processor, check if it's
> off phase, and reset it if it is.
>
> Since these are cmos static processors, there should be a deterministic
> method of starting the processor in a particular phase on MCLR.
>
> -Adam
>
> Daniel Sweet wrote:
>
> >Hi, Thanks for the reply.
> >
> >
> >
> >
> >>I read this thread, but I thing that using an external 40MHz clock
> >>won't have any difference in your problem. If you lock the 40MHz
> >>clock to your external source, then you don't known in which cicle
> >>the PIC is running.
> >>
> >>
> >
> >When at 40Mhz it always locks into exactly the same point of the cycle. I am not 100% certain that this will be the correct cycle but from what I have seen using a 40Mhz oscillator module it should be. Or have I misuderstood what you are saying? Can you explain a little more?
> >
> >You need to phase-lock the internal PIC cicle to your external clock.
> >
> >
> >>If I needed something as you describe, I'd try generating in the PIC
> >>a stable signal at hscan freq. (i.e. from an internal PIC timer) and
> >>using that to phase lock the main oscilator. It's simpler than it seems.
> >>
> >>
> >>
> >
> >It has to be locked to the 15.625Khz Hsync coming from the camera (via sync separator) as this signal does vary and causes all sorts of picture wobble. I do generate hsync in the PIC exactly and have tried to feed this into the ext divide of the Genlock IC to stabilise, but the one I generate is too perfect when compared the camera sync and the differences between them are too great for my PLL to correct them (don't know how well i explanied that, hope it makes sense)
> >
> >Cheers,
> >DAN
> >
> >--
> >http://www.piclist.com hint: The list server can filter out subtopics
> >(like ads or off topics) for you. See http://www.piclist.com/#topics
> >
> >
> >
> >
> >
>
> --
> http://www.piclist.com hint: The list server can filter out subtopics
> (like ads or off topics) for you. See http://www.piclist.com/#topics
>

--
http://www.piclist.com hint: The list server can filter out subtopics
(like ads or off topics) for you. See http://www.piclist.com/#topics