I am not sure!!

I can definetly see it is exactly related the PLL lock. How this causes the effect on the monitor o/p I am struggling with at the moment. I think I have avoided latency effects on a lot of the interrpts by careful timings and lots of NOPS (it ain't pretty!). 100ns is a very important amount of time in this project, it makes all the difference!

Any suggestions on how the internal PLL arrangement could have a latency effect? Tipping the balance of a transition between instruction cycles I assume...

Cheers,
DAN
>
> From: "Alan B. Pearce" <A.B.Pearce@RL.AC.UK>
> Date: 2003/06/12 Thu AM 11:18:52 GMT
> To: PICLIST@MITVMA.MIT.EDU
> Subject: Re: [PIC]:3rd Overtone- Now: [Pic]: HS/PLL issues when Genlocking to Video sync
>
> >What i see with my application is that only 1 of these 4
> >positions will work correctly. Not easy to explain the fault
> >but in the other 3 positions I can see on the TV monitor
> >that the vertical graticule i generate will have a kink in
> >1 or two places of 100ns (1 instruction Cycle).
>
> Are you sure this is not a 1 instruction variation in the interrupt latency?
> How can you be sure.?
>
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