> -----Original Message-----
> From: Alan B. Pearce [SMTP:A.B.Pearce@RL.AC.UK]
> Sent: Wednesday, June 04, 2003 9:50 AM
> To:   PICLIST@MITVMA.MIT.EDU
> Subject:      Re: [EE]: Zilog Encore series microprocessors
>
> > I developed an interrupt-driven software UART in a previous application,
> > but I wasn't happy about sampling each incoming data bit at less than 8x
> > rate, which in this case would be 153kHz for 19,200baud.
>
> Why? The only time you really need to do this is during the start bit, and
> then use an interrupt on the leading edge of the start bit, and time a
> half
> bit time, then make sure it really is a start bitn not a noise glitch, and
> then sample every bit time, making sure there is a valid stop bit finally
> to
>
> > On the other hand, a hardware UART would only interrupt the processor at
> > a maximum rate of 1.9kHz.
>
> And using the above scheme that is what will happen for a software uart,
> except at the beginning of the start bit.
>
Actually, the processor will be interrupted at the bit rate using the above
method, i.e. 19.2KHz.  Typicaly for a robust software UART, the bit would be
sampled multiple times (as the OP stated) which puts the interrupt rate back
up to silly levels.

Regards

Mike


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