>    This reminds me of a question I've been meaning
> to ask.  Some UART code I've seen checks TRMT=1,
> other code checks TXIF=1, and some code checks both
> flags.  Is there a reason why just checking TXIF=1
> to verify that TXREG is empty is not sufficient?

The basic difference is that TXIF is part of the interrrupt system.
TRMT is not and has to be polled by code. In some applications
it may be advantageous to have comms interrupt-driven. The
example I gave came from a dedicated routine that had a push-
button entry, so there was no other s/w competing for attention
during comms so testing TRMT was sufficient

TXIF and TRMT are indicators for two registers, TXREG and TSR

TXIF shows the condition of TXREG. When TXIF=1 TXREG is
available for new data, ie the data previously in TXREG has been
moved to TSR (and so on to the comms line)

TRMT shows the condition of TSR. When set it indicates that TSR
is empty (MT) and that the data has been sent out

> Under what circumstances would you need to know that
> that the TSR itself is empty before sending another
> character?

TXREG can be loaded with new data (according to TXIF) even if
there is data still in TSR. The PIC won't transfer the new data from
TXREG to TSR until the previous data send is complete. Referring
back to example I posted, testing TRMT - and knowing that no new
data has been loaded into TXREG - tells you that the transmit module
is empty. In a handshake situation you could then wait for a data
request from the other device, possibly by enabling RCIF interrrupts
if the requests are unpredictable

That's my quick precis of some aspects of the TX part of the UART
in Asynch mode. It's covered in more detail in Section 10.2 of DS30292
(F877 manual) and Section 18.4.1 of DS31018 (Midrange Reference
Manual)

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