> IN ---|>o-----)|------|>o------ OUT
>                    |
>                    |_---/\/\/\/\--- GND
>
> To me, the capacitor is acting as a coupling capacitor, so I fail to see
> how this is making the output a small pulse given the input state.  Can
> someone explain how this is producing a digital pulse on the output?

The C and R form a high pass filter into the second inverter.  In a rough
sense, this means edges get thru but steady levels don't.

Start with the circuit with IN high and steady state.  IN goes low, causing
a rising edge into the capacitor.  This step is coupled immediately to the
output inverter, making it go low.  So far, the signal has just been passed
thru.  Now consider what happens as IN stays low.  The input to the
capacitor stays high, but the output will exponentially decay towards 0.
This decaying voltage will eventually be interpreted as a low input by the
second inverter, making it go high.  We have so far sent a falling edge in
and gotten a low going pulse out.  In other words, and edge to glitch
converter.

Now IN goes high.  This causes the input to the capacitor to go low.  The
output of the capacitor is already at 0, so it will attempt to go to -5V.
However, the input clamping diode in the second inverter will clip that
to -700mV or so.  The output is not changed, but now we're ready for IN to
go low again and cause another pulse.

This type of circuit is somewhat of a kludge.  Wanting an edge to glitch
converter is usually a symptom of bad design elsewhere.  Note also that the
second inverter should be a schmitt trigger unless the RC time constant is
very low.

As an additional exercise, consider what the circuit does if R and C are
exchanged.


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