What you have here is a "differentiator".  You are correct, no DC will get
through the capacitor.

But consider: initially, assume the input is high, thus the output of the
1st inverter is low. The input to the 2nd inverter is also low due to the
resistor, and thus the output of the 2nd inverter is high.

Now, the input goes low, the output of the inverter goes high, as does the
voltage on the left side of the capacitor. Since the voltage across the
capacitor cannot change instantaneously, the voltage on the right side of
the capacitor will go high also. The output of the 2nd inverter will now go
low.

As the capacitor charges through the resistor, the voltage on the input to
the 2nd inverter will start to drop exponentially - the time this will take
depends on the values of the resistor and capacitor. As the voltage drops,
it will reach a value that causes the 2nd inverter to think it's input is
now low, so the inverter output goes high.

Voila - a pulse, whose width depends on the values of R and C, and on the
voltage at which the 2nd inverter will change state. This pulse appears on
the falling edge of the input waveform.

When the input voltage goes high, the 1st inverter will go low; the right
side of the capacitor will follow suit, since the voltage can't change
instantaneously. Since the capacitor will have been fully charged by this
time (the voltage on its right side will be zero), the voltage on the right
side will go -ve, and will slowly increase towards zero as the capacitor
discharges through the resistor. This -ve voltage on the input of the 2nd
inverter will just leave the inverter's output high, thus there will be no
output pulse.

So what happens: on the rising edge of the input pulse, the output stays
low. On the falling edge of the input pulse, there will be a short pulse at
the output. So you have generated a pulse delayed by the width of the input
pulse.

Larry

At 11:56 AM 4/19/2003 -0400, you wrote:
>Hello,
>
>I have seen used in some circuits a delay pulse when a particular input
>signal does high.  I.E.  The output of the circuit generates a short
>pulse of 200 us when the input logic state goes 0, but then the output
>goes high again even when the input is still low.
>
>I can seen to figure out how this is working.  The circuit is a simple
>inverter + a series capacitor to another inverter.  Also from the input
>of the second invertor, between it's pin on the output of the capacitor,
>a resistor is used to pull the pin to ground. The circuit looks
>something like this:
>
>IN ---|>o-----)|------|>o------ OUT
>                    |
>                    |_---/\/\/\/\--- GND
>
>To me, the capacitor is acting as a coupling capacitor, so I fail to see
>how this is making the output a small pulse given the input state.  Can
>someone explain how this is producing a digital pulse on the output?
>
>When I look at the circuit, it seems like no DC logic signal will get
>through to the output.  When the input is low, the capacitor will charge
>through the resistor.  Which leaves the output of the capacitor still at
>ground level, correct?  Then when the input is high again, this causes
>an instantaneous discharge of the capacitor, still leaving the output of
>the capacitor at ground level, so I fail to see how this is used as a
>way to generate a fixed length pulse when the input goes low.
>
>What am I missing?
>
>Regards,
>
>James
>
>
>
>--
>http://www.piclist.com hint: The PICList is archived three different
>ways.  See http://www.piclist.com/#archives for details.

Larry Bradley
Orleans (Ottawa), Ontario, CANADA

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