Hi,

thanks for the replies,
Alan B Pearce wrote:
>Is the slave implementation the same as the 16F87x series? If the =
register
>bits look the same than I would work on basing my code around the
>application note code from microchip (AN734 IIRC). I did this to do an
>interrupt driven slave, and it works quite nicely, especially as I got =
the
>note from someone about the error in the app note code, before I =
started
>trying to use it.

I was actually trying to use that as an base but found it had errors ;)
and that it was lacking a few features I needed (see below).
But eventually I did use it, removed the errors and added some minor =
tests.

Michael Rigby-Jones wrote:
>I have coded a slave for a 16F877 which worked fine on an 18 series.  =
You
>don't (normaly) need to check for start/stop condtions, the way I
>implemented it was as a very simple state machine.
<snip>

and Barry Gershenfeld finally commented:
>What I found was that Start and Stop don't cause any interrupts.
>That's because the hardware takes care of this, and there isn't
>anything the program needs to know about them.
<snip>

Well this case is a bit special, I think I need to know
both the start and stop conditions (particulary stop) as
I need to do some data processing after the message is recived.
The final program will emulate an Philiphs LCD driver chip
but add an hoist of additional features (MMC-card gateway, Realtime
clock, LED display support (7segment)).=20
I haven't seen an clearcut way to signalise that the data from
the master is complete without hooking onto the stop condition.
Or are there other ways ?=20

I coded an framework yesterday, but I'll refrain to post
it until I've had an chance to run it. But as soon as I see it
operating according to my specification I'll post it.

But basiclly I ended up with the following states and order:
(remember that start/stop also generates irq )

Entry:
1
        ; SSPSTAT bits: S=3D1, P=3D0, D_A=3D0, R_W=3D0, BF=3D0
        ; start condition detected
2
        ; SSPSTAT bits: S=3D0, P=3D1, D_A=3D0, R_W=3D0, BF=3D0
        ; stop condition detected
3
        ; SSPSTAT bits: S=3D1, P=3D0, D_A=3D0, R_W=3D0, BF=3D1
        ; write operation and last byte was adress
4
        ; SSPSTAT bits: S=3D1, P=3D0, D_A=3D1, R_W=3D0, BF=3D1
        ; write operation and last byte is data
5
        ; SSPSTAT bits: S=3D1, P=3D0, D_A=3D0, R_W=3D1, BF=3D0
        ; read operation and last byte was adress
6
        ; SSPSTAT bits: S=3D1, P=3D0, D_A=3D1, R_W=3D1, BF=3D0
        ; read operation and last byte was data
7
        ; SSPSTAT bits: S=3D1, P=3D0, D_A=3D1, R_W=3D0, BF=3D0
        ; master issued an nack while we were transmitting data

Is this order or are the conditions incorrect ?

/Tony

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