It seem to remember seeing somewhere that *any*
instruction modifying PCL, takes 2 inst cycles.
That is, any instruction whos net result is that
the CPU can *not* execute the instruction in the
next higher address (that is already loaded into
the instruction pipeline/cache).

And I don't know what happens if you add 0 to PCL. That
isn't a "branch" realy.
It might invalidate the cache pipeline anyway, and then
just re-load the same instruction again (and taking an extra
instr cycle).

/Jan-Erik S=F6derholm.

shoppa_piclist@TRAILING-EDGE.COM wrote:

>The data sheet tells me that CALL, GOTO, and taken BTFSS and BTFSC's
>take two instruction (8 clock) cycles, and that's great.  But it also
>tells me that ADDWF only takes one cycle, yet a ADDWF PCL,F is
>truly a branch so I'd naively expect it to take two, and the =
instruction
>fetch diagrams lead me even further to suspect that it will take two.
>What's the real story here?

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