Hi All,

I'm working in my free time on a nice experimental & educational design,
using the PIC (16F877 of 18F458) as a powerline modem.
The main idea is like this:

Transmitter - FSK modulation, four signal frequencies from range 120 to 140 kHz.
  The "power amplifier" - 6 CMOS inverters working in parallel, the output
  signal is fed to the power line through the LC band-pass filter, to eliminate
  higher frequencies resulting from the square waveform.

Receiver - The received signal is separated from the powerline voltage using
  the band-pass filter (active RC+OAMP filter), then downconverted to the
  10kHz-30kHz range by multiplying by the 110kHz frequency signal.
  The resulting LF signal is then sampled by the PIC, and digitally
  processed by the PIC (using the very simple "filter bank" algorithm)
  to detect the level of particular signal component.

The problem I've faced is that I'm unable to output waveforms with two
different "hardware generated" frequencies.
Theoretically I have a lot of timers (3 in 16F877 or 4 in 18F458), but
unfortunately I'm not able to route their output to the pins (except of
Timer 2, using the PWM). Well I can use the SCK pin to output the internally
generated frequency, but this is Timer 2 again :-(.
There is the USART with the TX/CK pin, but I'd prefer to reserve it for host
communication...

In fact if it would be possible to output three different frequencies, then
even simpler system could be built:
Two signal frequencies (f1 & f2) could be used, and then the received,
filtered signal should be submitted to "quadrature detection" on both
f1 and f2 frequencies. (Very easy to do if you can generate the 2*f1 and
2*f2 frequencies - the simplest "quadrature detector" could consist of
two D flip-flops, two CMOS switches and RC LP filter). The output from
quadrature detector should then be sampled by the PIC's ADC and processed to
recover the digital data.

However the main problem is how to generate the square waves with the
programmable frequency... Can it be done with the CCP module? (I need only
one edge to be jitter free - all external circuits can be "raising slope
triggered", so the jitter of the failing edge does not matter at all).

Could it be done as follows?
Both CCP work in "compare, set output on match" mode (0x1000).
After each CCPxIF interrupt, the pin CCPx is reset by software, and the new
CCPRx value is calculated as follows: (PULSE_LENx - the period of the
square wave)
   CCPRx = (CCPRx + PULSE_LEN) modulo 0x10000

Thank you in advance for any hints or sugestions, regarding both - PLC modem
idea and the PIC related problems I've faced.
--
                Regards,
                Wojciech Zabolotny
                wzab@ise.pw.edu.pl

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