At 07:02 PM 2/4/2003 -0500, you wrote:
>I am holding the CS pin low until the end of the 500ms delay.
>
>Clock is strobed with CS and DI pin at a logic 0
>CS and DI are then taken high, then the clock is strobed again to set the
>start bit.
>After that, DI is toggled as required to send the opcode while the clock is
>strobed.
>
>Should I hold CS high during the 500ms delay?

No, sorry, I mixed this up with the 25xx series devices I've been using
lately.
CS should be held low. It may not be an issue, but I always make sure there
are no internal pullups enabled and add an external pull-down resistor in
cases like this.

>  I thought the 93LC46A toggled
>on the positive going edge... do I have that backwards??  Figured i would
>keep everything low until ready for use, clock in one cycle with CS and DI
>low, then clock in one cycle with CS and DI high to send start bit.

Yes. +ve edge on CLK is for data in/out. You're meeting the timing
requirements?
Note a rather slow 400nsec between CLK +ve edge and valid data at the output.

>The ORG should be OK... the 46A has no ORG, it is always 8 bit.

Microchip's is like that, anyhow. I think Fairchild and ST's 46A's *do* have
the ORG pin.

Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

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