I am holding the CS pin low until the end of the 500ms delay.

Clock is strobed with CS and DI pin at a logic 0
CS and DI are then taken high, then the clock is strobed again to set the
start bit.
After that, DI is toggled as required to send the opcode while the clock is
strobed.

Should I hold CS high during the 500ms delay?  I thought the 93LC46A toggled
on the positive going edge... do I have that backwards??  Figured i would
keep everything low until ready for use, clock in one cycle with CS and DI
low, then clock in one cycle with CS and DI high to send start bit.

The ORG should be OK... the 46A has no ORG, it is always 8 bit.

> Do you hold /CS high for the 500ms before attempting to access the EEPROM?
>
> Are the clock and data pins in the same state at the point where /CS goes
> low?
>
> Are you sure there is no issue with the ORG input on some 93xx46's -
> these parts vary SIGNIFICANTLY from manufacturer to manufacturer.
>
> Best regards,
>
> Spehro Pefhany --"it's the network..."            "The Journey is the
reward"
> speff@interlog.com             Info for manufacturers:
http://www.trexon.com
> Embedded software/hardware/analog  Info for designers:
http://www.speff.com

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