Thanks Bob Ammerman and Scott for the explanation
Regards
Luis F.




> On Fri, 31 Jan 2003, Bob Ammerman wrote:
>
> > ----- The following code is directly from the multiply/divide code
generator
> > at:
> >
> > http://www.piclist.com/techref/piclist/codegen/constdivmul.htm
> >
> > This routine assumes the input value, in ACC is in the range 0..4095. In
> > other words, the high order four bits are zeros:
> >
> > ; ACC = ACC * 16
> > ; Temp = TEMP
> > ; ACC size = 12 bits
> > ; Error = 0 %
> > ; Bytes order = little endian
> > ; Round = no
> >
> > ; ALGORITHM:
> > ; Clear accumulator
> > ; Add input * 16 to accumulator
> > ; Move accumulator to result
> > ;
> > ; Approximated constant: 16, Error: 0 %
> >
> > ;     Input: ACC0 .. ACC1, 12 bits
> > ;    Output: ACC0 .. ACC1, 16 bits
> > ; Code size: 6 instructions
> >
> >         cblock
> >         ACC0
> >         ACC1
> >         endc
> >
> > ;shift accumulator left 4 times
> >         swapf   ACC1, f
> >         swapf   ACC0, f
> >         movf    ACC0, w
> >         andlw   0x0F
> >         xorwf   ACC0, f
> >         iorwf   ACC1, f
>
> I was wondering when someone would suggest this type of solution!
>
>
> >
> > ----- If the 4 high bits of ACC may not be zero, then you can make the
> > following sneaky tweak to the previous code, adding one instruction:
> >
> > movlw    0x0F
> > andwf    ACC1,f
> > swapf ACC1, f
> > swapf ACC0, f
> > andwf ACC0, w
> > xorwf ACC0, f
> > iorwf ACC1, f
>
>   Yep! or many other variations of the theme:
>
>     swapf  ACC0,f   ; low byte
>     movlw  0x0f
>     andwf  ACC1,f
>     swapf  ACC1,f   ; high byte
>     andwf  ACC0,w
>     xorwf  ACC0,f
>     xorwf  ACC1,f
>
> (Wouldn't a barrel shifter be nice about now?)
>
> >
> > ---- Note that the four high order bits of the result are chopped off
> >
> > ---- Finally, for the divide by 8 the code generator comes up with:
> >
> > lrc
> >         rrf     ACC1, f
> >         rrf     ACC0, f
> >         clrc
> >         rrf     ACC1, f
> >         rrf     ACC0, f
> >         clrc
> >         rrf     ACC1, f
> >         rrf     ACC0, f
>
> doesn't this need another clrc at the beginning? If this snippet is to be
> followed by the shift left by 4 snippet, then the last instruction (in the
> shift left) can be change from an xor to an add. This will clear the
> carry. If they're not contiguous, then the shift right by three can be
> implemented in 8 instructions like:
>
>    rrf   ACC1,f
>    rrf   ACC0,f
>    rrf   ACC1,f
>    rrf   ACC0,f
>    rrf   ACC1,f
>    rrf   ACC0,f
>    movlw '00011111'b
>    andwf ACC1
>
> Scott
>
> --
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