Quoting Olin Lathrop : > > > You should do a bus STOP here, followed by a bus START before the next > > > command. > > > > Regarding this, in the command sequence diagram, it shows just to just > send a > > BUS Start bit, not stop and start. I was doing this, but neglected to > mention > > it. > > That should be OK. All devices are supposed to reset their bus logic on a > start, regardless of what state it was in at the time. In multi-master > mode doing just a start is actually a good idea so that no other master > can get in there between commands. > > > And yes, on the ninth clock cycle, I set the TRIS bit so that SDA > becomes an > > input. > > You should do that in the low phase before the ninth clock cycle, not "on" > the ninth clock cycle (whatever that means). > > > That's how it seems to get pulled low successfully. > > Huh? Setting the TRIS bit should cause SDA to float high. Something is > very wrong if setting the TRIS bit causes SDA to go low. My mistake (again). SDA doesn't get pulled low BEACUSE of the TRIS bit. All I meant was that I know I was setting the TRIS bit at the right time since it was successfully getting pulled low by the Slave :-) Like I mentioned, when I changed the address to something not of the slave, it didn't respond by pulling it low, so that's how I know the TRIS part is ok. I am afraid that it might be something in my reading sequence that is wrong - but I'm not sure what. > > > ***************************************************************** > Embed Inc, embedded system specialists in Littleton Massachusetts > (978) 742-9014, http://www.embedinc.com > > -- > http://www.piclist.com hint: The PICList is archived three different > ways. See http://www.piclist.com/#archives for details. > ---------------------------------------- This mail sent through www.mywaterloo.ca -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.