> > You should do a bus STOP here, followed by a bus START before the next
> > command.
>
> Regarding this, in the command sequence diagram, it shows just to just
send a
> BUS Start bit, not stop and start. I was doing this, but neglected to
mention
> it.

That should be OK.  All devices are supposed to reset their bus logic on a
start, regardless of what state it was in at the time.  In multi-master
mode doing just a start is actually a good idea so that no other master
can get in there between commands.

> And yes, on the ninth clock cycle, I set the TRIS bit so that SDA
becomes an
> input.

You should do that in the low phase before the ninth clock cycle, not "on"
the ninth clock cycle (whatever that means).

> That's how it seems to get pulled low successfully.

Huh?  Setting the TRIS bit should cause SDA to float high.  Something is
very wrong if setting the TRIS bit causes SDA to go low.


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