> I think you *don't* want the cap there.  It will slow down
> the rise to open circuit voltage and hold the panel at
> inefficient voltages for too long.  Yes, the energy produced
> by the panel during the test is captured, but overall energy
> production is diminished.

I'm two days behind, but how about keeping the capacitor there
and taking two samples instead of one to determine where you
are on the charging curve for the known capacitor?  The more
power available from the panel, the faster the voltage will
rise across the capacitor, etc...  In that sense, you would
measure the power from the panel with the voltage rise.  More
complicated, but it would reduce the overall powerloss.

Please note that I'm not an EE and I'm still learning about
circuit design.  If Roman and the other electronic wizards did
Not mention this idea, there's probably a reason.  Some that
spring to mind: KISS principle of overcomplicating a good
design, math too hard to quickly compute appropriate SMPS
control factors from this type of measurement on a standard
PIC because of all the floating point math, and maybe it's
just too bloody weird.


Brian Smith
Software Engineer qualified to push buttons, not soldering iron

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