First, a moderate amount of background: I'm trying to design my own programmer(and software) for the PIC that will be useable on most Linux systems without requiring root. Because of that restriction, it's natural to try to use the serial port; in fact, I've run across programmer designs that manage to power the entire thing off a capacitor charged by bouncing TX back and forth, all the while bit-banging the programming protocol with the RTS and DTR lines. (the software I've found still uses direct ioport calls to bit-bang the control lines, but presumably that could be rewritten to use the TIOCMBIS and related ioctl calls, which can be done without root priveleges and are portable beyoind x86 machines) I like the idea of powering the programmer off the supplied serial voltage, but bit-banging via the control lines just seems wrong when there's already a line (TX) that's dedicated to sending data anyway. So my plan is to have a programmer that can detect the start bit coming down the TX line, use that (positive-going) transition to trigger a monostable that will supply the clock transition downward at the appropriate time in the middle of the byte; then I'd send a series of 0xff and 0x00 bytes to the programmer, with each byte getting to the pic as one bit. The RTS/DTR control lines could then be used to power the programmer; holding them at opposite levels should give at least a 20 volt potential difference. (end background) Now, as I'm lazy, I assumed "someone must have done this before and posted it to the web; I'll start with their design". A brief google search (pic programmer "start bit") found this page: http://www.bubblesoftonline.com/projects/prog.html That design seems a good enough starting point - but to modify it, I have to understand how it works. This is where I get into trouble. I don't understand how the device shown can work at 1200 baud; it seems that it should work fine at 600 baud, and my question is basically: what's wrong with my calculations? The pin numbers below refer to the labeled nand gate pins; though the page doesn't mention it, the writer appears to be using a 74HCT132 or related chip. Let's look at a 0x00 byte being transmitted, since that's the more difficult case. To figure out where in the transmitted byte the downward clock edge falls, first I look at the voltage on pin 2. After the up-edge of the start byte, voltage at pin 2 should follow: V_2 = 5.1 * exp(- t /(100E-9 * 15E3)) = 5.1 * exp(-t/(1.5E-3)) Now, since the 74HCT132 has a (typical) downward-going threshold of 1.67 V, this means that the output at pin 3 will go high at 1.67E-3 seconds after the edge of the start bit. (the repetition of 1.67 here is pure coincidence: 1.67E-3 = -ln(1.67/5.1) * 1.5E-3 ) So the output of pin 3 looks like: before TX start edge: high immediately after TX start edge: low after 1.67E-3 seconds: high again (where it stays until the next positive transition on TX) Now, at 1200 baud 1.67E-3 seconds is just over two bits wide. The circuit between pins 3 and 6 is essentially the same as the circuit to the left of pin 2, but with a three times larger resistor. Therefore, the output at pin 4 will go high 6 bits after pin 3 goes high. This means that the downward edge of the clock pulse (pin 10) happens 8 bits after the start edge transmission. Now notice that the suggested protocol for this programmer is serial communication 7N1 - that is, eight bits after the leading edge of the start bit falls right when TX is making the transisition from high to low for the stop bit. Not good. The signal diagrams on that same page suggest that the intention was to have the downward clock pulse occur about 4 bits after the leading edge of the start bit. This would work just fine with the given resistance and capacitance values if the baud rate were 600. However, as it stands I'm left wondering whether I slipped a factor of two somewhere in my own calculations (being very new to designing my own circuits, and not having an oscilliscope to watch the waveforms with). So have I done my calculations right? Is this programmer off by a factor of two? If not, where'd I slip? Of course, once I figure this out there's the whole question of getting a reasonable signal to come down RX for the return data, but I think I have that worked partially worked out. (The difficult part is getting the RX stop bit to happen, which may require a third RC delay circuit) -- http://www.piclist.com hint: PICList Posts must start with ONE topic: [PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads