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Scott Dattalo wrote:
> You may wish to consider investigating:
>
> http://www.dattalo.com/technical/software/pic/picsine.html
>
> This sin() routine takes as its input a 14-bit frequency variable.
> (Scale 2^14 to 2*pi). Assign two 16-bit frequency variables to your
> 14kHz and
> 14.25 kHz frequencies. Advance each of these by a fixed (but
> different) amount in a timer based interrupt routine and call the
> sine routine mentioned above.
>
> The sine routine takes 48 cycles. If you based your frequencies on a
> TMR0 interrupt with the pre-scale = 1, you could easily run both of
> these routines (~100 cycles out of the 256).
>
> Choosing the update rate:
>
> Let's suppose you're running your PIC off of a 20MHz clock. That's
> 20/4 = 5 million cycles per second. A TMR0 interrupt can be
> programmed to occur every 256 / 5million = 51.2 uS. The period of a
> 14,000 Hz wave form is
> 71.42 uS. Oops. This ain't gonna work :(.
>
> ---
>
> Phase accumulators but no linear interpolation:
>
> The routine on my web page uses phase-accumulator techniques for the
> frequency variable (phase accumulator is just fancy term for rollover
> arithmetic) and linear interpolation for the sine computation. The
> linear interpolation takes quite a bit of time. So Eric Smith's sine
> computation is more suitable for your application:
>
> http://www.brouhaha.com/~eric/pic/sine.html
>
> His code will take about 13 cycles. Again, you'll want 16 bit phase
> accumulators for the frequency variables. Using Eric's code, it would
> take about 13*2 + 4*2 ~ 34 cycles to compute the two sine values. On
> a 20MHz pic will take 6.8 uS or roughly 10.5 samples per sine wave.
> The challenge now is designing the isochronous code to update at this
> rate. (You can make the TMR0 interrupt run fast than 256 cycles by
> manually writing to it.)
>
> ---
>
> A pure software technique sounds iffy. But as Michael asks, it really
> depends on your requirements. There is one more software technique
> using ADPCM but it would consume all of the PIC's resources.
>
> Scott

Dear Moonshadow,


You said the second generator will go from 14 to 14.25kHz in 10kHz steps, is
quite strange, isn't it?  Are you sure it is not 10Hz increments?

You also said jitter about 4.99% or less is accepted. Hmmm. 14kHz 5% jitter is
720Hz, are you sure?

One should never forget about sinewave frequency double easy implemented with an
analog multiplier. Four of those little chips can give you the flexibility to
quadruple both sine waveforms at the uCs output.

Two chips gives you original frequency times 4.  Of course, if the filtering is
not good, then it doesn't matter in anyway, since the original errors will also
multiplied by 4. But if the processor power is a problem, then the multiplier
chips can help.



One need to remember that to a analog multiplier double a frequency, the input
signal should travel to a negative region, quadrantes 3 and 4.  It can be
acomplished by several means, small transformers, capacitor coupling, etc.  The
third sinewave above (higher frequency) required to offset the second sinewave
at half and subtract half of its value to get the desired 4x input frequency.
Also note, that the job of an analog amplifier is not just double the quadrants
3 and 4 to 1 and 2 as a diode bridge would do. The diode bridge would leave
sharp peaks by folding the sinewave in middle, the zero crossing makes a sharp
fold.  The analog multiplier just multiplies and will resulting a nice and
smooth zero crossing folding.

It is very difficult to get precise 10kHz increments in a binary system running
14kHz sinewave output. The multipliers could help you, since you will be running
sine at 3.5kHz only, but you should consider binary than decimal increments.

You could also think about implement an analogic sine generator, frequency
controlled by digital means.
There are some sine generators, one old guy that comes to mind is the 8038.  You
could control the frequency by uC digital means, and by a closed loop feedback
measuring and correct the frequency.

The use of a sine table can be speed up by using a double external ADC or even a
R2R 8 bits output resistor ladder in two 8 bits port.  Running at 4MIPS you can
get a max output around 2MSamples/second.  Suppose a 256 entries table and
scanning it at 64 levels (read 1 step 3), it means 31250kHz, but hard to control
precisely 10Hz (if this is the case).

/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Wagner Lipnharski - UST Research Inc
Orlando FLorida - USA - www.ustr.net
/_/_/_/ Atmel AVR Consultant /_/_/_/

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