Thanks for your reply...I am continuing my debugging. About your
comments, there actually is more to the code that I have deleted. Your
comments about bank switching are valid, but the bank bits are saved and
cleared at the start of the ISR. As all my variables are in the first
bank, I don't think I need to mess with any of the banking bits in my
ISR, unless there is a SFR that I've got wrong somewhere. In addition,
there are more options in the interrupt polling section that aren't
relevant, so I snipped them as well. The SRESET pin is being cleared
properly, but it is always set again right away. Do you see anything
wrong with my zero checking at that point?

Thank you for your ideas and suggestions.

Josh
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Olin Lathrop wrote:
>
> > Well, that's how it is supposed to work...in theory. In practice it
> > never gets past the first value. I can see the slave strobing the SRTS
> > line, so it would appear that the slave is receiving the first value.
>
> OK, so trace from there.  Set a breakpoint in the master interrupt routine
> and see what it's doing.  With such a major and repeatable symptom it
> should be easy to find why it's not advancing to the next byte.
>
> > I
> > thought perhaps the TMR0 interval on the master was too short causing
> > premature reset. Disabling the TMR0 (after the first iteration) causes
> > the master to wait forever for a response from the slave, or so it seems
> > anyway. It just sits there never putting new data on the bus. Actually,
> > a closer look just now with my scope seems to show a constant assertion
> > of Strobe, which in theory should be impossible.
>
> In theory it should work too, but obviously there is a bug.  Again, these
> symptoms sound like they are practially handing you the problem on a
> silver platter.  Go trace the code from the last known correct point and
> see what it's screwing up.
>
> > ; Define slave controls
> > #DEFINE                            S1Reset              PORTB, 1
> > #DEFINE                            S2Reset              PORTB, 2
> > #DEFINE                            S1Strobe             PORTB, 3
> > #DEFINE                            S2Strobe             PORTB, 4
> > #DEFINE                            INT0INTERRUPT        PORTB, 0
> >
> > IN ISR
> >
> > IH_Interrupt_Poll
> >
> >         btfsc   INTCON, INTF
> >          goto   IH_INT0_Trigger
> >         btfsc   INTCON, T0IF
> >          goto   IH_TMR0
>
> Are you really really sure you'll always get one of these interrupt
> conditions?  If you don't, it will fall thru to the INT0 interrupt
> handler.  I usually jump to 0 here.  There may not be any right answer,
> but it should cause obvious symptoms and provides a good place to trigger
> on if you suspect it is happening during debugging.
>
> > IH_INT0_Trigger
> >         bcf             INTCON, INTF            ;Clear INT0 flag
>
> You need to set the bank here.  It doesn't matter for INTCON, but does
> matter for PORTB.
>
> >         bcf             S2Reset                 ;Clear Reset line
>
> This is a good thing to test with the scope.  Is the reset line being
> cleared?
>
> >         movf    TRANSCNT, F
>
> Bank settings again.
>
> >         btfsc   STATUS, Z                       ;If we're at 0
> >          bsf            S2Reset                 ;assert Reset line
> >
> >         movlw   PWM00VAL                        ; Start at the location
> of
> >         addwf   TRANSCNT, W                     ;PWM00VAL, then add
> >         movwf   FSR                             ;the value of TRANSCNT
> as
> >                                                 ;offset for FSR
>
> Now you need to watch the indirect bank setting.
>
> >         movf    INDF, W                         ;Put value in INDF on
> >                                                 ;PORTD, data bus
> >         movwf   PORTD
>
> It is pointless to continue until banking is addressed.  Check out my
> DBANKIF and related macros in STD.INS.ASPIC at
> http://www.embedinc.com/pic.

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