Hi all. I'm at my wit's end with this problem. I've been hacking away at it for about a week. I've found a bunch of problems which have subsequently been fixed (mainly stupid mistakes on my part). I can't seem to see anything else wrong now though, and I'm sure it's because I've been staring at it too long. In essence, here is what I am trying to do. Eventually, there will be three PICs, one master and two slaves. At the moment I'm just trying to get it to work with one master and one slave. I am attempting to transfer 8 bytes of data from the master to the slave. The master is a 16f877 running at 20MHz, and the slave is an 18f252 running at 40MHz. Everything else seems to be running fine on these chips, except of course the actual data transfer. In addition to the actual 8 bit data bus, there are three pins as flow control. I will call them SRTS, Strobe, and Reset. Strobe is asserted by the master when valid data is present on the bus. It is connected to INT1 on the Slave, and configured as a low priority interrupt (high priority interrupts are used for more important things). If the byte of data that the master is transmitting is the first byte (byte0), then the Reset line is asserted. It is polled by the slave during the data read. The SRTS line is asserted by the slave when it has read the data bus. It is connected to INT0 on the master. When the slave has read the data, it strobes the SRTS line which throws the master into the ISR, and the master increments to the next data byte. There is a timer (TMR0) on the master that triggers if it hasn't received a response from the slave in time. It basically resets the counters and tries again. Well, that's how it is supposed to work...in theory. In practice it never gets past the first value. I can see the slave strobing the SRTS line, so it would appear that the slave is receiving the first value. I thought perhaps the TMR0 interval on the master was too short causing premature reset. Disabling the TMR0 (after the first iteration) causes the master to wait forever for a response from the slave, or so it seems anyway. It just sits there never putting new data on the bus. Actually, a closer look just now with my scope seems to show a constant assertion of Strobe, which in theory should be impossible. I don't know, perhaps at this point I'm measuring wrong. Anyway, to make this long post even longer, I will include the pertinent portions of my code. I'm sorry for the supersized post, I'm really at a loss at the moment though. Master Code (snipped and trimmed, of course) ; Define slave controls #DEFINE S1Reset PORTB, 1 #DEFINE S2Reset PORTB, 2 #DEFINE S1Strobe PORTB, 3 #DEFINE S2Strobe PORTB, 4 #DEFINE INT0INTERRUPT PORTB, 0 IN ISR IH_Interrupt_Poll btfsc INTCON, INTF goto IH_INT0_Trigger btfsc INTCON, T0IF goto IH_TMR0 IH_INT0_Trigger bcf INTCON, INTF ;Clear INT0 flag bcf S2Reset ;Clear Reset line movf TRANSCNT, F btfsc STATUS, Z ;If we're at 0 bsf S2Reset ;assert Reset line movlw PWM00VAL ; Start at the location of addwf TRANSCNT, W ;PWM00VAL, then add movwf FSR ;the value of TRANSCNT as ;offset for FSR movf INDF, W ;Put value in INDF on ;PORTD, data bus movwf PORTD bsf S2Strobe ;Strobe Slave2 Strobe line nop ;to throw it into ISR nop nop nop bcf S2Strobe incf TRANSCNT, f ;Increment transmission ;counter movlw d'9' ;Check to see if we've subwf TRANSCNT, w ;sent all 8 values btfsc STATUS, Z ;to the slaves goto IH_TRANS_Reset ;If so, go to reset ;transmission goto IH_Exit IH_TMR0 bcf INTCON, T0IF ;Clear TMR0 flag clrf TRANSCNT ;If TMR0 has elapsed, slave hasn't ;responded in time, so reset count ;and try again goto IH_INT0_Trigger IH_TRANS_Reset ;Reset everything to neutral value clrf TRANSCNT bcf S1Reset bcf S2Reset bcf S1Strobe bcf S2Strobe clrf PORTD goto IH_Exit IN MAINLINE ; Initialize timer 0 bsf STATUS, RP0 ;Bank 1 bcf OPTION_REG ^ 0x080, T0CS ;Internal Clock ;cycle bcf OPTION_REG ^ 0x080, PSA ;Prescale to TMR0 bsf OPTION_REG ^ 0x080, PS2 ;Prescale value of bsf OPTION_REG ^ 0x080, PS1 ;1:256 bsf OPTION_REG ^ 0x080, PS0 bcf STATUS, RP0 clrf TMR0 ; Initialize interrupts CLRF INTCON bsf INTCON, T0IE ;Enable TMR0 Interrupt bsf INTCON, INTE ;Enable INT0 Interrupt BSF INTCON,PEIE ; Enable Peripheral Interrupts BSF INTCON,GIE ; Enable General interrupts Ok, that's the Master code, here is the slave code: ;Defines #Define LED1 PORTB, RB4 #Define LED2 PORTB, RB5 #Define STROBE PORTB, RB1 #Define SRESET PORTB, RB2 #Define SRTS PORTB, RB0 IN ISR INT1_INT btg LED2 ;toggle LED for testing btfsc SRESET ;Test for reset line clrf CHANCNT ;If first value, clear count movf PORTA, W ;Combine data on PORTA and PORTE andlw b'00111111' ; to get 8 bit value, place in movwf PWMTEMP ; PWMTEMP movf PORTB, W andlw b'11000110' iorwf PWMTEMP, F movf CHANCNT, W ;Use channel count as offset. I movwf FSR0L ; can do this because my Channel movff PWMTEMP, INDF0 ; value variables start at 0x0000 ;Should change for final version incf CHANCNT,F ;Increment channel count bsf SRTS ;Strobe SRTS to throw master into nop ;ISR <10 NOPs snipped for size> ;Tried up to 12 NOPs to get master ;to recognize them...no result. nop bcf SRTS bra End_ISRL IN MAINLINE bsf RCON, IPEN ;Enable interrupt priority ;levels bsf INTCON2, TMR0IP ;TMR0 is a high priority ;interrupt bsf INTCON2, INTEDG1 ;INT1 is on rising edge bcf INTCON3, INT1IP ;INT1 is low priority bcf INTCON3, INT1IF ;Clear INT1 interrupt flag bsf INTCON3, INT1IE ;Enable INT1 interrupt bsf INTCON, GIEH ;Enable High interrupts bsf INTCON, GIEL Ok, I think this post is monster enough. I would really appreciate any help...I've worked through the code a number of times, and I can't see why it isn't working right. I'm sure I'm just missing something stupid...but I have no clue what it is. Thanks in advance, (a very desperate) Josh -- A common mistake that people make when trying to design something completely foolproof is to underestimate the ingenuity of complete fools. -Douglas Adams -- http://www.piclist.com hint: PICList Posts must start with ONE topic: [PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads