> (This is an Eagle schematic and board file, all zipped up.)
    > I'm interested in suggestions of all sorts,

    * Nice job on the schematic symbols for the 4 digit displays.  Did you
    make those yourself?

Yes, I did.  Thanks!  (Unfortunately, they're not quite complete, as I
confirmed when actual parts reached my hands.  The symbols will get a bit
uglier when the missing pins get defined.  Sigh.)


    * Either smash a symbol and move its label or don't cram things so close
    together that the labels can't be read.  Neatness counts.  Use more sheets
    if you have to.

It's the freeware version, so I'm limitted to one sheet.  I have a "real
problem" with "density" vs readability, especially when it comes to text.
I used some of the DIN TTL symbols in another schematic, and they were HUGE
compared with (for instance) the PIC symbols.  For the resistors here, I
tried to delete most of the lables, but it seems that if you smash and
delete both name an value, you get unsmashed text back when you redisplay.
(I think there were some suggestions of moving the smashed text to
undisplayed layers on the Eagle newsgroups - I'll try that.)


    * The crystal caps should go to GND, not VDD, although it will probably
    work fine this way.

Yes, I started a discussion on that topic a while back.  Still, in this
case, I'm not sure I need to use VCC - that part of the schematics was
copied from a single-layer board where the crystal placement and wiring
was more critical.


    * A bunch of parts don't have values, like C1, C2.  Again neatness and
    attention to detail count.

Noted.

    * I don't follow what's going on with the fat traces (polygon?) on the top
    layer around the two displays.  This seems to be overlaying a whole row of
    pads.  There are several instances of this sort of thing.

As a signal-bearing polygon, these automatically "retract" to the isolation
distance (relatively large on my boards) from all other signals when you do
a rats-nest operation to "fill" the polygons. (The 'filled' status of
polygons doesn't seem to get saved, though.)  The top-layer polygon you
mention does have a different line width than the other polygons for no good
reason, though.  I'm usually not very careful about fine placement of the
polygon, since the 'real' copper gets computed.  Should I be?


    * Don't let the silkscreen get onto the pads.  It can act like a solder
    mask.

Ah.  I thought I was careful with this, but I see problems over by the
connectors for inbound signals.  I should probably rework those "packages",
since the current text placement is particularly badly suited toward the
obviously-shaped arrays of "wires."

BillW

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