To understand addressing in the 18F you need to know what an address looks
like in the instruction itself.

Unlike the 16F, where addresses were stored as only 7 bits in the
instruction; in the 18F addresses are stored as 2 separate fields: a 1-bit
field call the "ram access bank" and  an 8-bit field called the "file
register address".

These two fields are combined as follows to determine the effective address
of the file register to be used:

if the "ram access bank" bit is a 1 then

    the effective address is BSR:"file register address".
    In other words, the effective address is constructed
    using BSR to provide the high order 4 bits and
    8 bits from the instruction to provide the low order
    8 bits. This allows you to access 256 bytes in the
    bank pointed to by BSR.

else if the high bit of the "file register address" is a 0 then

    the effective address is just the file register address. This
    allows access to the first 128 bytes of memory regardless
    of the setting of BSR.

else (the high bit of the "file register address is 1) then

    the effective address is X'F':"file register address. This
    will result in addresses in the range X'F80' through
    X'FFF', which are the SFRs.

end if

> Also, when defining data RAM (equ or cblock), how do I define the
> registers in BSR=0x01? Do I have to offset them and give them a higher
> value (.128+), or do they map to .1+?

The assembler will by default access any register in the ranges
X'000'..X'7Fh' or X'F80' using the "access bank". Otherwise, the assembler
will assume that the specified register is in the bank currently pointed to
by the BSR.

So, that means that your variables in bank 1 should be declared as being at
addresses X'100' through X'1FF'.

Bob Ammerman
RAm Systems

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