Did anyone respond to this yet? The bad tag may have had something to do
with it.

"Rad R. Rad" <rad0@ATTBI.COM> wrote:
> If any of you can help to decipher the data sheet for the
> image processor chip, I would be greatly appreciative.
>
> http://www.lh.co.nz/hardware/ar/techinfo.htm
>
> I'm doing this with a stamp for the time being, and I'm pretty
> much confused between the description of how it describes how to
> do a reset, for example, and between what the timing diagrams show
> that you need to do.
>
> for example in the reset, the data sheet tells you that 'the reset
> sequence completes when both the Xrst and RESET signals are set low.'
>
> This seems to be saying that you hold both of these signals low, and
> this will reset the chip.
>
> However, the timing diagram shows the Xrst and RESET signals as
> begining high, then going low, with the clock (Xck) signal pulsing
> above, then the Xrst and RESET resuming high again.
>
> So, in other words it shows that the Xrst And RESET signals just need
> to be pulsed low, to get a reset.
>
> Which is it?  Am I getting wound up over the way this thing is worded?  Do
> you most usually 'pulse' these type of signals?  And I'm not sure if
> you have to send a pulse to the RESET pins while you clock the clock.

It appears that two areas of the chip ("system" and "parameter memory") can
be reset independently.

Both reset inputs are synchronous; if either one is low when a rising edge
of the clock occurs, the corresponding area will get reset. If you want to
reset the entire chip, you can pull both resets low on the same clock edge,
as shown in their timing diagram.

You're probably getting confused because most chips have asynchronous reset
inputs, which don't need a clock.

-- Dave Tweed

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