> Sherlock Holmes tells us that therefore the code is wrong! (probably :-) ) > Most probable cause is that you haven't allowed for the time spent in the > ISR when reloading the counter. > If so the clock will be slow by about > > (time in ISR)/(Time between interrupts). He is using timer 2 with the hardware period register, not timer 0. You're right though about adding into timer 0 when using it to divide the clock by other than 256. Also take into account the number of cycles timer 0 stops when written to. Back to the original problem. One possibility is he is setting PR2 to 250 instead of 249. I would have given more detail before, but my reply looked messy enough due to his insistance on using quoted printable. ***************************************************************** Embed Inc, embedded system specialists in Littleton Massachusetts (978) 742-9014, http://www.embedinc.com -- http://www.piclist.com#nomail Going offline? Don't AutoReply us! email listserv@mitvma.mit.edu with SET PICList DIGEST in the body