Wagner Lipnharski <wagner@USTR.NET> wrote:
> Dave Tweed wrote:
> > A ripple counter is made of flip-flops that change state on the
> > high-to-low transition of the clock. So, because of causality, a
> > given stage has to go low before the stage that it drives can go
> > high. As a result, you can never see a count that is "too high", even
> > as a glitch; you'll only see glitch values that are too low.
> > Therefore, this method of creating a programmable divider works just
> > fine.
>
> If you observe the time diagram below, where each division output is
> delayed a little bit, you will see that (in this particula example), the
> 8th clock bit missis completely the F raise, and F should raise at the 8th
> A bit.

Well, yes, but in this example, you're clocking the counter far too fast,
where "too fast" in this case means a clock period much shorter than the
overall propogation delay of the part. A min-max timing analysis of the
counter+gate combination would show that the output of the gate is *never*
valid.

-- Dave Tweed

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