Dave Tweed wrote: > No, and if you think about it a bit, you'll see why. > > A ripple counter is made of flip-flops that change state on the > high-to-low transition of the clock. So, because of causality, a > given stage has to go low before the stage that it drives can go > high. As a result, you can never see a count that is "too high", even > as a glitch; you'll only see glitch values that are too low. > Therefore, this method of creating a programmable divider works just > fine. > > -- Dave Tweed If you observe the time diagram below, where each division output is delayed a little bit, you will see that (in this particula example), the 8th clock bit missis completely the F raise, and F should raise at the 8th A bit. In this example, due the extreme delay from A to F, an imaginary 74HC00 with A and F at the inputs, will only activate output when A=10, since F raises only after (same time) of dropping of 9th A. It means, an hipotetical AND A.F would identify A.F = 10 and not 9 as expected. Of course, the internal delays between stages can gives you only DELAYS and LOWER Counts. 1 2 3 4 5 6 7 8 9 10 11 12 13 _ _ _ _ _ _ _ _ _ _ _ _ A_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ | ___ ___ ___ ___ | ___ ___ B| |___| |___| |___| |___| |___| |____ | _______ _______ | _______ C_____| |_______| |_______| |___ | _______________ | __ D______________| |_______________| | _________________ F_______________________________| A A | | | | Count of "9" should happens HERE | when F and A should be HIGH. | | But in this example, it happens HERE at count of "10" due internal propagation delays. Wagner. -- http://www.piclist.com hint: PICList Posts must start with ONE topic: [PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads